Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a data bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line (or a pair of bit-lines), which is used for storing a data bit into a selected SRAM cell or reading a stored data bit from the selected SRAM cell.
A register file is an array of processor registers in a central processing unit (CPU). Integrated circuit-based register files are usually implemented by way of fast SRAMs with multiple ports. Such SRAMs are distinguished by having dedicated read and write ports, whereas ordinary multi-ported SRAMs will usually read and write through the same ports.
With the scale of integrated circuits decreasing, the operation voltages of integrated circuits are reduced and similarly the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which are used to measure how reliable the data bits of the SRAM cells can be read from and written into, respectively, are reduced. Due to the existence of static noise, the reduced read and write margins may increase the possibility of errors in the respective read and write operations.
For single ended sensing of a memory cell, the precharged local bit-line either stays at the precharged level or it is discharged to ground level depending on the data that is stored in the bit-cell. When the local bit-line is kept floating during the case where the cell does not have the data value to discharge the local bit-line, the leakage from the pass gates (all cells in one column) discharges the local bit-line to zero during low frequency operation, thus making a false sensing. To avoid this false sensing issue, the local bit-line is kept at Vdd through a weak (small current) precharger device, i.e. a “keeper” circuit.
FIG. 1 illustrates a conventional sense amplifier circuit 100 that can be a portion of a SRAM array or register files, and includes a keeper circuit 102. The size of components of the keeper 102 is very critical in order to assure that the bit-cell overpowers the keeper 102 for a normal read operation. The circuit 100 is connected to bit-lines, i.e. top bit-line 108a and bottom bit-line 108b. The precharger 110 charges the local bit-line 108a and 108b to high state according to the control signals 114 when there is no read operation. During manufacturing of the memory as disclosed in FIG. 1, there are acceptable variations in performance parameters. Process corners refer to integrated circuits with lowest and/or highest desirable performance parameters. Skew corners refer to integrated circuits with both lowest and highest desirable performance parameters in their sub-circuits. At low voltages, and skew corners (e.g. slow array transistors in bit-line 108a or 108b and fast periphery transistors in a keeper 102), the bit-cell connected to the bit-line 108a or 108b will not be able to overpower this keeper 102. Therefore, there is a limitation on the lowest desirable power supply voltage, i.e. Vdd_min, for the circuit to operate without error.
One way to make this circuit 100 work properly under low voltage is to increase the resistance of the keeper 102, such as increasing the channel length of the keeper transistor 104 or decreasing the width of the same. This will make the keeper 102 easier to be overcome by the bit-cell connected to the bit-line 108a or 108b. However, this method has its limits due to the area that the keeper transistor 104 occupies and also the current flow level necessary for the keeper 102 to provide the leakage current from the pass gates and thus make it operational.
Another way to make the circuit 100 operational under low voltage is to make the trip point voltage of the NAND gate 106 higher, where the trip point is the highest voltage where the sense amplifier output at output node 112 switches from a high level to a low level. For that purpose, for example, when the NAND gate 106 comprises NMOS and PMOS, the value of β of the NAND gate 106 can be increased, where β is the ratio of Wp/Wn, and Wp and Wn are the gate widths of PMOS transistor and NMOS transistor, respectively. This ratio β determines the trip point in CMOS circuits. However, this will make the circuit 100 susceptible to noise closer to the high state voltage because the trip point is higher. For example, when there is noise in the bit-line 108a or 108b close to a high state, the output voltage could be lowered by the noise below the trip point of the NAND gate 106, which triggers an erroneous operation.
Therefore, methods to avoid false sensing the local bit-line under low voltage for SRAM and/or register files are desired.